The present invention relates generally to methods for manufacturing transistors and integrated circuit devices comprising multiple transistors. In particular, the invention relates to p-type metal-oxide-semiconductor (PMOS) devices and methods for manufacturing such devices. The invention relates most particularly to field effect transistor (FET) devices, including PMOSFET devices, and the manufacture of such devices. The invention comprehends both discrete PMOS devices, or PMOS devices included in integrated circuit devices.
There are two major types of FET devices, the metal-oxide-semiconductor field effect transistor or MOSFET (also called an insulated-gate FET, or IGFET), and the junction-gate FET, or JFET. An FET has a control gate, and source and drain regions formed in a substrate. The control gate is formed above a dielectric insulator that is deposited over the area between the source and drain regions. As voltage is applied to the control gate, mobile charged particles in the substrate form a conduction channel in the region between the source and drain regions. Once the channel forms, the transistor turns xe2x80x9conxe2x80x9d and current may flow between the source and drain regions.
Transistors are used as either amplifying or switching devices in electronic circuits. In the first application, the transistor functions to amplify small ac signals. In the second application, a small current is used to switch the transistor between an xe2x80x9conxe2x80x9d state and an xe2x80x9coff state.xe2x80x9d
In recent years, the computer industry has experienced extremely rapid growth in all aspects, including number of units produced, breadth of applications, power and speed of operation, and complexity of competing machines. This growth is attributable to many factors, including remarkable increases in the number of active devices (typically transistors) included in the integrated circuit devices used in computers. By increasing the number of transistors in an integrated circuit device, the size of a computer may be reduced, or a more complex computer may be made within a particular computer case size. In addition, by increasing the number of transistors in an integrated circuit device, operational problems such as cross talk between physically adjacent conductors and signal propagation delays between different sections of the computer can be reduced. Further, integrated circuit devices are typically less expensive and more reliable than counterparts manufactured from discrete components. For these and many other reasons, the use of integrated circuit devices of increasing size and complexity has become the standard of the computer industry.
The trend toward more complex integrated circuit devices has resulted in increasing density of individual devices within the integrated circuit devices. To increase the number of individual devices within an integrated circuit, it is necessary to decrease the size of each individual device. The size of individual devices cannot be reduced arbitrarily. There are limitations to size reduction, including dimensional tolerance capabilities associated with manufacturing processes and various electrical phenomena that are associated with physical dimensions of the device. In addition, the essential need for high reliability of integrated circuit devices places limitations on shrinking the size of such devices. The steps of identifying these and other limitations and discovering techniques for ameliorating these limitations have made possible the increasing complexity of integrated circuit devices.
The prior art in the field of manufacture of PMOS devices has numerous examples of identification of problems that occur during manufacture and subsequent usage of such devices. The art also has examples of proposed solutions to the identified problems. A brief summary of some of the relevant patent art is provided below.
U.S. Pat. No. 4,420,872 issued to Soledad de Zaldivar teaches the use of nitrogen ion implantation to create a silicon nitride-containing layer as a mechanism to mask FET devices against undesired silicon oxidation during manufacture. U.S. Pat. No. 4,774,197 issued to Haddad et al. teaches the use of nitrogen ion implantation into the polycrystalline silicon gate of an FET which, during subsequent high-temperature causes a formation of silicon nitrides at the interface between the gate and the underlying gate insulation, and at the interface between the gate insulation and the underlying silicon substrate. This structure makes the gate insulation more nearly defect-free and more reliable in service.
U.S. Pat. No. 5,330,920 issued to Soleimani et al. teaches the use of nitrogen ion implantation as a mechanism to control gate oxide layer thickness. The patent teaches growing a sacrificial oxide layer on the surface of a silicon substrate, implanting nitrogen into the substrate through the sacrificial layer, removing the sacrificial layer, then growing a gate oxide layer. Where the nitrogen had been previously implanted into the substrate, the rate of gate oxide layer growth is reduced.
U.S. Pat. No. 5,468,657 issued to Hsu and U.S. Pat. No. 5,589,407 issued to Meyyappan et al. each teach the use of nitrogen ion implantation in conjunction with the growth of buried oxide layers that comprise the insulator in silicon-on-insulator (SOI) wafers used in manufacturing complementary metal-oxide-semiconductor (CMOS) devices. U.S. Pat. No. 5,908,312 issued to Cheung et al. teaches the implantation of atomic nitrogen into the silicon substrate before the growth of an oxide gate insulating layer. The patent specifically states that atomic nitrogen is the preferred species for this purpose, as opposed to molecular nitrogen.
Five recent patents, assigned to a common assignee, have taught the importance of threshold voltage in MOS transistor devices, and have described ways to control that voltage. These five patents are U.S. Pat. Nos. 5,674,788; No. 5,893,739; No. 5,909,622; No. 5,851,893; and No. 5,861,335. In the first of these patents, Wristers et al. teach that an oxynitride gate insulation layer reduces the likelihood of diffusing boron from the gate into the channel region lying below the gate. The oxynitride layer also reduces the trapping of electrons in the gate insulator. Wristers et al. also teach that the oxynitride layer is advantageously grown in situ by using a growth atmosphere that contains nitrous oxides, nitric oxides, or both.
The next two patents describe the deleterious effects of hot carriers, whether holes or electrons, that can accumulate in the gate oxide layer and raise the threshold voltage of the MOSFET device. The transistors produced according to the of these two patents feature asymmetrical construction, with a wider barrier between the gate and drain than between the gate and source. Gardner et al. teach a mechanism to control hot carrier effects by injecting barrier atoms into the silicon beneath the gate edge near the drain. Hause et al. teach implanting nitrogen into the silicon substrate on either side of the channel region, where such implantation is done concurrently or after the doping of the source and drain regions.
The existence of a threshold voltage is an inherent characteristic of MOSFET devices. In the case of a PMOSFET, a high threshold voltage signifies that the device is readily turned xe2x80x9con,xe2x80x9d meaning that holes flow from the source to the drain. A practical consequence of a high threshold voltage is that the PMOSFET has a greater current-driving capability, which implies a higher speed of logic level transitions. Thus, high threshold voltages in PMOSFET devices are desirable to increase the operating speed of digital circuits. Conversely, a high threshold voltage increases the susceptibility of the device to current flow between the source and drain when the gate voltage is less than the threshold voltage; that is when the device operates in a sub-threshold regime. Also, a PMOSFET having a high threshold voltage typically has less immunity to electrical noise and has higher contribution to the chip standby current resulting from an increase in channel xe2x80x9coff current.xe2x80x9d
These effects are described in greater detail by Wristers et al. in U.S. Pat. No. 5,674,788 at Column 1, Lines 13-54, which disclosure is incorporated herein by reference. Fortunately, the threshold voltage of a PMOSFET device can be controlled by choices in the physical design of the device and by choices of manufacturing process parameters. As a general rule, PMOSFET devices are typically designed and manufactured to have a high threshold voltage, subject to constraints relating to the intended application of the devices.
Research leading to the present invention has indicated that a PMQSFET device may have a threshold voltage characteristic of the sidewall corner regions of the channel (identified in FIG. 1 at 64 and 66) that is different from the threshold voltage in the main section of the gate between the two sidewalls (identified in FIG. 1 at 68). The sidewall corner regions of the channel are identified at the interface between the device isolation substance and the single crystal silicon along the channel. The contribution of these regions to the sub-threshold conduction can be conveniently visualized as that of a parasitic sidewall corner PMOSFET acting in parallel with the main PMOSFET device. There may exist a situation where the threshold voltage of the main section may be low enough so that there is virtually no contribution to the channel xe2x80x9coff currentxe2x80x9d from this region, while the threshold voltage of the sidewall corner PMOSFET device is high enough to permit significant xe2x80x9coff current.xe2x80x9d In the extreme case, the xe2x80x9coff currentxe2x80x9d through the sidewall corner device can be great enough for the electrical output of the device to be interpreted as xe2x80x9conxe2x80x9d even though from the input signal to the gate the electrical output should be xe2x80x9coff.xe2x80x9d The role of the sidewall comer region in controlling xe2x80x9coff currentxe2x80x9d behavior had not been known before the present invention.
Research leading to the present invention has also shown that the channel xe2x80x9coff currentxe2x80x9d of a PMOSFET device can be affected by the operating conditions of the device. In particular, a phenomenon called xe2x80x9chot carrier degradationxe2x80x9d produces electron trapping localized in the gate-drain region of the device, this phenomenon causes an increase in the threshold voltage of the device and, therefore, and increase in channel xe2x80x9coff current.xe2x80x9d Although this effect can occur at any location along the junction between the gate and drain, it is most acute in the gate-drain-sidewall corner region. Hot carrier degradation may result, therefore, in the activation of the parasitic sidewall corner device increasing the xe2x80x9coff currentxe2x80x9d channel contribution. Hot carrier degradation may be either temporary or permanent. It affects operating characteristics of the device, constrains the methodologies for effective bum-in coverage, and limits aggressive use of the device.
Recognizing the considerable likelihood of PMOSFET devices having high threshold voltages in their sidewall corner regions, it is an object of the present invention to provide such devices that have reduced sensitivity to threshold voltage increases during operation and burn-in in their sidewall comer regions. It is also an object of the present invention to provide a method for manufacturing such devices. It is another object of the present invention to provide PMOSFET devices that have reduced sensitivity to parasitic sidewall comer activation and to hot carrier degradation that may take place during burn-in and use conditions.
It is a further object of the present invention to provide such technologies for both buried channel and surface channel PMOSFET devices. It is yet another object of the present invention to provide such technologies for PMOSFET devices having either thick or thin gate oxide layers, or even dual gate oxide layer thicknesses. Still other objects and advantages of the present invention will be obvious or apparent from the detailed description of the invention provided in this specification.
The method of manufacture of the present invention, as described below, accomplishes these and other objects through a combination of design concepts and embodiments of those concepts. The method is applicable to the manufacture of PMOSFET devices, both discrete devices and devices incorporated into integrated circuits. Similarly, devices manufactured in accordance with the teachings of the present invention accomplish the objects set forth above and other objects.
The essence of the present invention is implanting a low-energy dose of nitrogen at the interface along the channel region between the silicon substrate and the isolation substance before the growth of gate oxide insulation. This manufacturing process reduces the hot carrier-induced activation of parasitic sidewall corner PMOSFET devices. The accomplishment of this improvement is not restricted to a localized nitrogen implantation along the sidewall corner area, but can also be achieved by a uniform nitrogen implantation into the surface of the silicon substrate of a PMOSFET device immediately before the growth of gate oxide insulation. Other steps in the process of manufacturing the PMOSFET device are substantially similar to practices commonly used in the industry. A PMOSFET device manufactured by this method is also part of the present invention, for some of its operational characteristics are unique to devices so manufactured.
Research leading to the present invention has indicated that the method is applicable to both single and dual gate technologies. It is also applicable to PMOS devices having either thin or thick gate oxide insulators, or gate oxide insulators that have both thin and thick sections. It is therefore intended by the inventors that this discussion of their invention, and the appended claims, be interpreted as specifically including the types of devices included in this paragraph, and other related devices.
It is understood that the foregoing summary and the following detailed description of the invention are exemplary, but are not restrictive, of the invention.